Design of Low Power Level-Converting Retention Flip-Flop using LSSR technique for Zigbee SoCs

In this paper, we propose the design of low power level-converting retention flip-flop (RFF)using LSSR technique for Zigbee System-onchips (SoCs).The proposed retention flip-flop allows the voltage regulator which generates the core supply voltage (VDD, core) is turned off during the standby mode and thus reduces the standby power and dc current of the Zigbee SoCs. This method is the combination of the feature of both, LECTOR approach and the forced stack technique. In LECTOR approach, the gate terminal is controlled by the source of the other. In forced stack technique, Transistors in PULL UP and PULL DOWN networks are replaced as two half sized transistors. In the proposed technique, two leakage control transistors will be added between the PULL UP and PULL DOWN networks. It will provide the limitation of area to preserve the circuit state during sleep mode. This technique will provide good